서강대학교-CAD & VLSI Research Laboratory

Prof. Juho Kim

- Prof. of department of Computer Science & Engineering, Sogang Univ.
- Prof. of graduate School of Information and Technology, Sogang Univ.
- Chief in ABEEK(Accreditation Board for Engineering Education of Korea) Center, Sogang Univ.

· Address

Sogang University, Ricci Hall(R 906A)

35 Baekbeom-ro(Sinsu-Dong), Mapo-Gu, Seoul, 04107, Korea

· Email

jhkim@sogang.ac.kr

· Tel / Fax

+82-2-706-3997

Educational Information

- B.S degree in Computer and Information Science, University of Minnesota at Minneapolis(1987)
- Ph.D degree in Computer and Information Science, University of Minnesota at Minneapolis(1995)

Career Information

- Senior Member of Technical staff at Cadence Design System(~1996.12)
- Assistant professor at the Department of Computer Science in Sogang Univ.(1997)
- Associate Professor at the Department of Computer Science in Sogang Univ.(2000)
- Full Professor at the Department of Computer Science in Sogang Univ.(2005)

Publications

· International Journal
Title	Publisher	Journal's name	Volume & issue	Date	No. of authors
Random Forest Based Thermal Aware Clock Tree Synthesis in 3D-IC	IEEE	JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE	Vol. 23 No, 3	2023.6	3
Thermal-aware 3D Symmetrical Buffered Clock Tree Synthesis	ACM	TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS	Vol. 24 No, 28	2019.6	3
Privacy protection mechanism for indoor positioning systems	INDIA PUBLICATIONS SUBSCRIPION	INTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH	Vol. 12 No. 9	2017.5	3
IT-dependent strategic initiative to increase the marketing performance of mobile security solutions	INDIA PUBLICATIONS SUBSCRIPION	INTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH	Vol. 12 No. 6	2017.4	2
Extracting the K-most Critical Paths in Multi-corner Multi-mode for Fast Static Timing Analysis	IEEE	JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE	Vol. 16 No. 6	2016.12	3
Enhanced-Precision LHSMC of Electrical Circuit Considering Low Discrepancy	SCIE	JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE		2015.2	3
Robust flip-flop Redesign for Violation Minimization Considering Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI)	ACSIJ	ADVANCES IN COMPUTER SCIENCE AN INTERNATIONAL JOURNAL	Vol. 1 No. 4	2015.1	2
Variation-Aware Aging Analysis in Digital ICs	IEEE	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS		2013.10	3
An Accurate Gate-level Stress Estimation for NBTI	SCIE	JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE	Vol. 13 No. 2	2013.4	4
A Performance and Usability Aware Secure Two-Factor User Authentication Scheme for Wireless Sensor Networks	HINDAWI PUBLISHING CORPORATION	INTERNATIONAL JOURNAL OF DISTRIBUTED SENSOR NETWORKS		2013.3	3
Software architecture of JTAG security system	WORLD SCIENTIFIC AND ENGINEERING ACADEMY AND SOCIETY	WSEAS TRANSACTIONS ON SYSTEMS	Vol. 11 No. 8	2012.8	3
Selective application of VPN by service using port number in SSL-based host-to-gateway VPN environment	SPRINGER VERLAG	LECTURE NOTES IN COMPUTER SCIENCE		2012.8	3
Debug Port Protection Mechanism for Secure Embedded Devices	IEEK	JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE	Vol. 12 No. 2	2012.6	3
Confidential information protection system for mobile devices	WILEY-BLACKWELL	SECURITY AND COMMUNICATION NETWORKS	Vol. 5 No. 12	2012.3	3
A security-performance-balanced user authentication scheme for wireless sensor networks	HINDAWI PUBLISHING CORPORATION	INTERNATIONAL JOURNAL OF DISTRIBUTED SENSOR NETWORKS		2012.2	3
DDoS avoidance strategy for service availability	SPRINGER	CLUSTER COMPUTING-THE JOURNAL OF NETWORKS SOFTWARE TOOLS AND APPLICATIONS	Vol. 16 No. 2	2011.10	4
Security requirements prioritization based on threat modeling and valuation graph	SPRINGER VERLAG	COMMUNICATIONS IN COMPUTER AND INFORMATION SCIENCE		2011.9	3
Specification-based intrusion detection system for WiBro	SPRINGER VERLAG	LECTURE NOTES IN COMPUTER SCIENCE		2011.9	4
Enhanced intrusion detection system for PKMv2 EAP-AKA used in WiBro	ASIAN NETWORK FOR SCIENTIFIC INFORMATION	INFORMATION TECHNOLOGY JOURNAL	Vol. 10 No. 10	2011.6	5
Timing Analysis Techniques Review for sub-30 nm Circuit Designs	IEEK	JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE	Vol. 10 No. 4	2010.12	3
JTAG Security System Based on Credentials	SPRINGER	JOURNAL OF ELECTRONIC TESTING -THEORY AND APPLICATIONS	Vol. 26 No. 5	2010.9	4
Clock Scheduling and Cell Library Information Utilization for Power Supply Noise Reduction	IEEK	JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE	Vol. 9 No. 1	2009.3	3
Stochastic Glitch Estimation and Path Balancing for Statistical Optimization	IEEE	IEEE International SOC Conference		2006.9	3
Efficient False Aggressors Pruning with Functional Correlation	IEICE	IEICE TRANS. FUNDAMENTALS	Vol. E87-A No. 12	2004.12	2
Unified low power optimization algorithm by gate freezing, gate sizing, and buffer insertion	CAP	Current Applied Physics		2004.7	3
Combining Transistor Sizing, Wire Sizing and Buffer Insertion to Low Power in CMOS Digital Circuit Design	JKPS	Journal of the Korean Physical Society	Vol. 42 No. 2	2004.7	2
Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design	IEICE	IEICE TRANS. FUNDAMENTALS	Vol. E85-A No. 1	2002.1	3
New Path Balancing Algorithm for Glitch Power Reduction	IEE	IEE Proc.-Circuits Devices Syst.	Vol. 148 No. 3	2001.6	2
A Post-Layout Optimization by Combining Buffer Insertion and Transistor Sizing	IEICE	IEICE TRANS. FUNDAMENTALS	Vol. E83-A No. 10	2000.10	2
Gate Sizing and Buffer Insertion Algorithm to ReduceGlitch Power Dissipation	IEEE	Journal of Electrical Engineering and Information Science	Vol. 5 No. 3	2000.6	2
Efficient Algorithm for Glitch Power Reduction	IEEE	Electronics Letters	Volume:35 Issue:13	1999.6	3
Interleaving Buffer Insertion and Transistor Sizing into a Single Optimization	IEEE	Very Large Scale Integration(VLSI) Systems, IEEE Transactions	Volume:6 Issue:4	1998.12	4
Combined transistor sizing with buffer insertion for timing optimization	IEEE	Computer Aided-Design of Integrated Circuits and Systems, IEEE Transactions		1998.5	4
Performance Optimization by Gate Sizing and Path Sensitization	IEEE	Computer Aided-Design of Integrated Circuits and Systems, IEEE Transactions	Volume:17 Issue:5	1998.5	2
Path Sensitization and gate sizing approach to low power optimization	IEEE	Electronics Letters	Volume:34 Issue:7	1998.4	3
Simultaneous Transistor Sizing and Buffer Insertion for Low Power Design	IEEE	Journal of EE and CS	Volume:2 Issue:6	1997.12	1

· Domestic Journal
Title	Publisher	Journal's name	Volume & issue	Date	No. of authors
다중 입력 변화의 시간적 근접성을 고려한게이트 지연 시간 모델	대한 전자공학회	전자공학회 논문지	제47권 제2호	2010.2	2
하드웨어 암호코어 기반 인증 시스템	대한 전자공학회	전자공학회 논문지	제46권 제1호	2009.1	4
크로스톡 회피를 위한 게이트 사이징을 이용한타이밍 윈도우 이동	대한 전자공학회	전자공학회 논문지	제44권 제11호	2007.11	2
통계적 최적화를 위한 확률적 글리치 예측 및 경로 균등화 방법	대한 전자공학회	전자공학회 논문지	제43권 제8호	2006.8	3
Mobile CORBA 환경에서 게이트웨이간의 경로 최적화 핸드 오프	한국 정보 과학회	정보 과학회 논문지	제29호 제3호	2002.6	3
글리치 전력 소모 감소를 위한 게이트 사이징과 버퍼 삽입 혼합기법	한국 정보 과학회	정보 과학회 논문지	제28권 제8호	2001.8	3
자연 제약 하에서 면적의 최적화를 위한 트랜지스터 사이징과 버퍼 삽입 알고리즘	한국 정보 과학회	정보 과학회 논문지	제27권 제7호	2000.7	2
저전력 CMOS 디지털 회로 설계에서 경로 균등화에 의한 글리치 감소 기법	한국 정보 과학회	정보 과학회 논문지	제26권 제10호	1999.10	4
회로 설계 검증을위한 스위치 - 레벨 이진 결정 다이어그램	대한 전자공학회	전자 공학회 논문지	제36-C권 제5호	1999.5	3
게이트 사이징과 감작 경로 검색에 의한 CMOS 디지털 회로의 저전력 설계 기법	대한 전자공학회	정보 과학회 논문지	제25-7권	1998.7	3
게이트 사이징과 최장 감작 경로를 이용한 클럭 주기 최적화 기법	대한 전자공학회	전자 공학회 논문지	제35-C권 제1호	1998.1	1

· Conference Proceedings
Title	Publisher	Journal's name	Volume & issue	Date	No. of authors
Timing Window Shifting for crosstalk avoidance in 3D-IC	IEEE	2023 INTERNATIONAL TECHNICAL CONFERENCE ON CIRCUITS/SYSTEMS, COMPUTERS AND COMMUNICATIONS (ITC-CSCC)		2023	4
Machine Learning based Gate Size Adjustment for Crosstalk Fault Tolerant in 3D-IC	한국 반도체 학술대회	제 30회 한국반도체 학술대회		2023	4
BTI-aware Cell Characterization based on Neural Network	IEEE	2022 CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS)		2022	3
Delay Impact on Process Variation of Interconnect throughout technology scaling	IEEE	2022 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)		2022	3
High level synthesis considering layer embedding on timing in 3D-IC	IEEE	2022 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)		2022	3
Machine Learning Based Path Delay Analysis Considering Crosstalk in 3D-ICs	한국 반도체 학술대회	제 29회 한국반도체 학술대회		2022	3
Learning-based Analysis of Aging Effects on Clock Tree Synthesis	한국 반도체 학술대회	제 28회 한국반도체 학술대회		2021	4
Symmetrical Buffered Clock Tree Synthesis Considering NBTI	IEEE	2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)		2020	3
The Construction of Look-Up Table based on Machine Learning for Static Timing Analysis	한국 반도체 학술대회	제 27회 한국반도체 학술대회		2020	4
The analysis of performance on clock tree topology using machine learning	반도체 학술대회	제 26회 반도체 학술대회		2019	4
The Impact of Slew in a Buffered Clock Tree Synthesis	반도체 학술대회	제 25회 반도체 학술대회		2018	3
The Clock Skew Analysis in Multi-corner Multi-mode	반도체 학술대회	제 25회 반도체 학술대회		2018	3
Thermal-aware clock tree topology for minimizing clock skew	반도체 학술대회	제 25회 반도체 학술대회		2018	4
Thermal-Aware 3D Symmetrical buffered Clock tree Synthesis	IEEE	2018 36th international Conference on Computer Design		2018	3
Fast Buffered Clock Tree Synthesis in Multi corner Multi mode scenario	대한전자공학회	INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC) 2018		2018	2
Slew-aware Fast Clock Tree Synthesis with Buffer Sizing	대한전자공학회	INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC) 2018		2018	3
Fast Parameterized Static Timing Analysis based on Branch and Bound Approach	대한전자공학회	제 24회 반도체 학술대회		2017	4
Performance optimization in FinFET-based circuit using TILOS-like gate sizing	IEEE	INTEGRATED CIRCUITS(ISIC),2016 INTERNATIONAL SYMPOSIUM ON		2016	3
LTE와 WiFi 연동을 위한 Multipath Aggregation 기술의 보안 동향	한국정보보호학회	2015 정보보호학회		2015	3
K-Critical Path Search Based Multi corner Multi mode Static Timing Analysis	IEEE	2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)		2014	4
몬테카를로 기반의 공정 변이를 고려한 회로 신뢰성 분석	대한전자공학회	춘계 SOC 학술대회		2014	3
High Level Synthesis considering NBTI Effect and Process variation on Timing	대한전자공학회	THE 13TH ICEIC 2013		2014	3
Fast Monte Carlo System for Yield Analysis using modified LHS	IEEK	THE 28TH ITC-CSCC 2013		2013	4
Security Enhanced IEEE 802.1x Authentication Method for WLAN Mobile Router	IEEE	14TH IEEE INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION TECHNOLOGY(ICACT2012)		2012	3
Variation-aware aging analysis with non-Gaussian parameters	대한전자공학회	SOC DESIGN CONFERENCE (ISOCC), 2011 INTERNATIONAL		2011	4
Statistical Aging Analysis with Process Variation Consideration	IEEE/ACM	2011 INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN		2011	6
Reliable Memory Encryption Scheme for Secure Embedded System	IEEK	THE 26TH INTERNATIONAL TECHNICAL CONFERENCE ON CIRCUIT/SYSTEMS, COMPUTERS AND COMMUNICATIONS		2011	3
NBTI-Aware Statistical Timing Analysis Framework	IEEE	23RD IEEE INTERNATIONAL SOC CONFERENCE		2010	2
Sleep transistor sizing through a path search and power gating considering delay for reducing leakage power	대한전자공학회	ICEIC 2010		2010	3
군용 임베디드 장치를 위한 데이터 보호 메커니즘	한국사이버테러정보전학회	제5회 한국 사이버테러정보전학회 춘계 학술대회		2010	3
누설전력감소를 위한 클러스터 기반의 파워게이팅	대한전자공학회	2010년 SOC 학술대회		2010	3
SERA: A Secure Energy and Reliability Aware Data Gathering for Sensor Networks	IEEE	INFORMATION SCIENCE AND APPLICATIONS (ICISA), 2010 INTERNATIONAL CONFERENCE		2010	3
Efficient Statistical Gate Delay Modeling with Aging Effects	대한전자공학회	제17회 한국 반도체 학술대회		2010	2
A Gate Delay Model Considering Temporal Proximity of Multiple Input Switching	대한전자공학회	2009 ISOCC		2009	5
Silicon Debug를 고려한 정적 전압레벨 오류 검출	대한전자공학회	2009년도 SOC 학술대회		2009	3
Efficient Cell Characterization for SSTA	IEEE	IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS		2008	3
Power Supply Noise Reduction by Clcok Scheduling with Gate-Level Current Waveform Estimation	IEEE	INTERNATIONAL SOC DESIGN CONFERENCE		2008	3
Secure Authentication Scheme using Digital Signature and Secure Key Storage	CENTER OF EXCELLENCE	2008 INTERNATIONAL CONFERENCE ON WIRELESS and INFORMATION TECHNOLOGIES		2008	4
Network Forensic Analysis Using Visualization Effect	IEEE	INTERNATIONAL CONFERENCE ON CONVERGENCE AND HYBRID INFORMATION TECHNOLOGY 2008		2008	2
멀티어그레서를 고려한 크로스톡회피 방법	대한전자공학회	2008년도 SOC 학술대회		2008	3
저전력 설계를 위한 분할 기법을 적용한 파워게이팅	대한전자공학회	15회 한국반도체학술대회		2008	3
Stochastic Glitch Elimination Considering Path Correlation	IEEE	IEEE INTERNATIONAL SOC CONFERENCE		2007	3
저전력설계를 위한 경로 상관관계를 고려한 확률적 글리치 예측 및 제거방법	대한전자공학회	2007 하계종합학술대회		2007	3
Statistical Optimization using Stochastic Glitch Estimation and Path Balancing	IEEK	ITC-CSCC		2007	4
Approximation of a Two Moments RC(L) Waveform Using Stochastic Approach	IEEK	International Soc Design Conference		2006	3
초미세 반도체 회로 설계를 위한 시간 분석	반도체 학술대회	13회 반도체 학술대회		2006	3
Slope 변이를 고려한 정확한 확률적 시간 분석	반도체 학술대회	13회 반도체 학술대회		2006	3
게이트 사이징과 버퍼 삽입을 통한 크로스톡 글리치 분석 및 제거	대한 전자 공학회	SoC 설계 연구회 학술 발표		2004	3
False Aggressors Pruning using the Path Sensitization for Crosstalk Noise Analysis	ITC-CSCC	International Technical Conference On Circuits/Systems, Computers and Communications		2004	2
Hierarchical Timing analysis using Functional Relations.	ITC-CSCC	International Technical Conference On Circuits/Systems, Computers and Communications		2004	3
Hierarchical Timing Analysis using Global False Path for Circuit Delay	반도체 학술 대회	제11회 한국 반도체 학술 대회		2004	3
Functional Aggressor Pruning by Path Sensitization for crosstalk Noise Analysis	반도체 학술 대회	제11회 한국 반도체 학술 대회		2004	2
단일화된 게이트 프리징, 사이징 및 버퍼 삽입에 의한 저 전력 최적화 알고리즘	반도체 학술 대회	제10회 한국 반도체 학술 대회		2003	3
An efficient wire sizing algorithm using uniform wire sizing formulation	반도체 학술 대회	제10회 한국 반도체 학술 대회		2003	3
Hierarchical Timing Analysis considering Global False Path	ITC-CSCC	International Technical Conference On Circuits/Systems, Computers and Communications		2002.7	2
Transistor sizing considering slew information to reduce glitch power in CMOS Digital Circuit Design	ITC-CSCC	International Technical Conference On Circuits/Systems, Computers and Communications		2002.7	2
저전력 최적화를 위한 트랜지스터사이징, 버퍼 삽입, 와이어 사이징통합 알고리즘	반도체 학술대회	제9회 한국 반도체 학술 대회		2002.2	2
Computer-Aided Design on Internet with Cryptosystem	IEEE	Systems, Man, and Cybernetics, IEEE International Conference	X	1998.10	4
International Symposium on Physical Design	KITE	ASIC Design Workshop	103-121	1997.7	1
Concurrent Transistor Sizing and Buffer Insertion by Considering Cost-Delay Tradeoffs	IEEE	International Symposium on Physical Design	130-135	1997.4	3
A New Gate Selection Method for Resizing to Circuit Performance Optimization	IEEE	International Symposium on Circuits and Systems	Vol. 4	1996.5	3
Derivation of Signal Flow Directions and Synchronizers for Switch-level Timing Analysis	IEEE	International Symposium on Circuits and Systems	Vol. 4	1996.5	3

· Books and translations
Title	Publisher	Date
나노 테크놀로지에서의 설계 방법론	홍릉과학출판부	2013.2
문제해결 프로그래밍	서강대학교 출판부	2005.12
예제로 배우는 자바2	기전 연구사	2000.9
비주얼 C++ 300제	기전 연구사	2000.8
VC++ 실습	기전 연구사	1998.5
예제로 배우는 JAVA	기전 연구사	1997.7
C를 배운다 윈도우 프로그래밍을 배운다	기전 연구사	1997.6
VC++와 윈도우 프로그래밍	기전 연구사	1997.5