• Research Areas

Our laboratory research areas :
- CAD (Computer Aided Design)

• CAD (Computer Aided Design)

Contemporary telecommunication device and computer are made by VLSI chip design. Such a VLSI is leading to the part of environment for chip design developing. CAD & VLSI of various research parts which are related to that is not the field which helping radical development of technology but the research part which has a broad application area. Recently so many mobile devices, likewise laptop, computer, mobile phone, PDA, and PMP, appearing to the world. hence the research of chip requiring ultra micro scale, High performance, and Low power is lively. So the role of CAD becomes more important.

A. Low Power Design
As a very large scale integrated of digital and analog circuit comes possible, the systems operate on each chip are able to operate together on only one chip. The importance of this researches are growing as we can see through cell phone, laptop computer which are popular device on our lives.

This devices are evaluated with running time with a same electric power or how much power dissipation are able to be reduced. therefore, in order to High performance - Low power design, the researches for optimized designs are in progress very actively like Gate Sizing Method, Glitch Reduction, Buffer Insertion.

B. Static Timing Analysis and Statistical Timing Analysis
The minimization of semiconductor process technology is making progress gradually at present. the affection of the progress variation that could be happen in semiconductor manufacturing process to semiconductor performance is relatively increasing, as semiconductor process has undersized smaller than 90 nano. This process variations are uncertain factors and they also need the probabilistic access and modeling. However, corner based and static timing analysis methodology of instance based that used to be used are not able to consider this is uncertain, and generally consider worst condition. therefore the results are not expected to be good. So now it is researching that statistical timing analysis which can probabilistic modeling and calculation.

C. Static Timing analysis in 3D-IC 

3D-IC (three-dimensional integrated circuit) refers to a technology in which multiple layers of integrated circuits are stacked vertically on top of each other to increase the packing density of the chips and to improve their performance. This technology involves bonding the layers of chips using through-silicon vias (TSVs) and microbumps, which allow for communication between the layers.

In the case of 3D-ICs, the timing analysis becomes more complicated due to the presence of multiple layers of chips. Each layer may have its own timing constraints and may affect the timing of the other layers. Therefore, the static timing analysis of a 3D-IC requires considering the timing of each layer individually and then analyzing the overall timing of the entire stack. Overall, static timing analysis is a critical step in the design and verification of 3D-ICs to ensure that the timing requirements of the circuit are met and to prevent timing-related issues such as data corruption or system failure.

D. Local Layout Effect (LLE) / Layout Dependent Effect (LDE)

The local layout effect(LLE) refers to the impact of the physical layout of a digital circuit on its performance. Transistors, wires, and vias, can affect the timing of the signals and introduce variations in the delay of the circuit paths.

The relationship between the LLE and STA is important because the physical layout of the circuit can have a significant impact on its timing performance. The variations in the delay caused by the layout can result in timing violations that are not detected by the STA, leading to a malfunctioning or unreliable system. To address this issue, the layout design must be optimized to minimize the impact of the local layout effect on the circuit's timing performance. Moreover, the STA must be performed with accurate and detailed models of the layout and timing parameters of the circuit to capture the local layout effects accurately. This requires the use of advanced simulation and modeling techniques, such as parasitic extraction, delay calculation, and interconnect modeling.